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1. general description the pcf8531 is a low-power cmos 1 lcd row and column driver, designed to drive dot matrix graphic displays at mult iplex rates of 1:17, 1:26, and 1: 34. furthermore, it can drive up to 128 icons. all necessary functions for the display are provided in a single chip, including on-chip generation of v lcd and the lcd bias voltages, resulting in a minimum of external components and low power consumpt ion. the pcf8531 is compatible with most microcontrollers and communicates via a two-line bidirectional i 2 c-bus. all inputs are cmos compatible. remark: the icon mode is used to reduce curr ent consumption. when only icons are displayed, a much lower operating voltage (v lcd ) can be used and the switching frequency of the lcd outputs is reduced. in most applications it is possible to use v dd as v lcd . 2. features and benefits ? single-chip lcd controller and driver ? 34 row and 128 column outputs ? display data ram 34 128 bits ? 128 icons (last row is used for icons) ? fast-mode i 2 c-bus interface (400 kbit/s) ? software selectable multiplex rates: 1:17, 1:26, and 1:34 ? icon mode with multiplex rate 1:2: ? featuring reduced current consumption while displaying icons only ? on-chip: ? generation of v lcd (external supply also possible) ? selectable linear temperature compensation ? oscillator requires no external componen ts (external clock also possible) ? generation of intermediate lcd bias voltages ? power-on reset (por) ? no external components required ? software selectable bias configuration ? logic supply voltage range v dd1 to v ss1 : 1.8 v to 5.5 v ? supply voltage range for on-chip voltage generator v dd2 and v dd3 to v ss1 and v ss2 : 2.5 v to 4.5 v ? display supply voltage range v lcd to v ss : ? normal mode: 4 v to 9 v pcf8531 34 x 128 pixel matrix driver rev. 6 ? 16 may 2011 product data sheet 1. the definition of the abbreviations and acronyms used in this data sheet can be found in section 19 .
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 2 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver ? icon mode: 3 v to 9 v ? low-power consumption, suitable for battery operated systems ? cmos compatible inputs ? manufactured in silicon gate cmos process 3. applications ? telecommunication systems ? automotive info rmation systems ? point-of-sale terminals ? instrumentation 4. ordering information table 1. ordering information type number package name description version pcf8531u/2da/1 - chip with bumps in tray -
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 3 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver 5. block diagram fig 1. block diagram of pcf8531 mgs465 display data ram matrix data ram data latches matrix latches column drivers c0 to c127 pcf8531 r0 to r33 row drivers command decoder address counter display address counter timing generator oscillator internal reset power-on reset enr res osc i 2 c-bus control input filters sa0 scl sda sdack v lcdout v lcdsense v lcdin t4 t3 t2 t1 34 v ss2 v ss1 v dd1 v dd2 v dd3 v lcd generator bias voltage generator 128
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 4 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver 6. pinning information 6.1 pinning viewed from active side. the positioni ng of the bonding pads is not to scale. fig 2. bonding pad location for pcf8531 mgs48 6 pad1 t2 t1 t3 scl sda osc res v ss1 v ss2 v lcdin v lcdout v lcdsense v dd1 v dd2 v dd3 enr sa0 sdack pcf8531 t4 x y 0, 0 c63 . . . . . . c127 . . . c64 . . . c31 . . . c32 . . . r32 . . . c0 . . . r0 . . . c96 c95 . . . r33 . . . r1 . . .
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 5 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver table 2. pad allocation table pad symbol pad symbol 15 osc 55 enr 16 v lcdsense 56 t4 17 to 23 v lcdout 57 to 63 v ss2 24 to 30 v lcdin 64 to 70 v ss1 31 res 71 t3 32 to 34 v dd3 72 t1 35 to 42 v dd2 73 to 74 scl 43 to 49 v dd1 78 t2 50 to 51 sda 87 to 103 r0, r2, r4, r6, r8, r10, r12, r14, r16, r18, r20, r22, r24, r26, r28, r30, r32 52 sdack 104 to 231 c0 to c127 54 sa0 232 to 248 r33, r31, r29, r27, r25, r23, r21, r19, r17, r15, r13, r11, r9, r7, r5, r3, r1 fig 3. alignment markers table 3. alignment markers for pcf8531 all x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see figure 2 ). alignment marks x ( m) y ( m) c1 ? 5402.0 823.1 c2 5292.4 950.0 f 5890.3 401.9 circle 1 ? 5543.0 798.4 circle 2 5637.4 798.4 mgs49 0 x center c 100 m x center circle 100 m 100 m 100 m x center f y center y center y center 80 m
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 6 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver [1] die size including saw lane of 70 m. 6.2 pin description fig 4. chip dimensions table 4. bonding pad dimensions pad size unit pad pitch (minimum) 70 m bump dimensions 50 90 17.5 ( 3) m wafer thickness (excluding bumps) 381 m die size l w 12.14 1.86 [1] mm 001aag90 8 x y l pitch w pcf8531 table 5. bonding pad description all x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see figure 2 ). symbol pad x ( m) y ( m) description - 1 5973.6 ? 821.7 dummy - 2 5969.5 823.4 - 3 5899.5 823.4 - 4 5829.5 823.4 - 5 5479.5 823.4 - 6 5409.5 823.4 - 7 5059.5 823.4 - 8 4989.5 823.4 - 9 4639.5 823.4 - 10 4569.5 823.4 - 11 4219.5 823.4 - 12 4149.5 823.4 - 13 3799.5 823.4 - 14 3729.5 823.4 osc 15 3449.5 823.4 oscillator input [1] v lcdsense 16 3169.5 823.4 voltage multiplier regulation input (v lcd ) [2]
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 7 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver v lcdout 17 3099.5 823.4 voltage multiplier output (v lcd ) [3] v lcdout 18 3029.5 823.4 v lcdout 19 2959.5 823.4 v lcdout 20 2889.5 823.4 v lcdout 21 2819.5 823.4 v lcdout 22 2749.5 823.4 v lcdout 23 2679.5 823.4 v lcdin 24 2539.5 823.4 lcd supply voltage (v lcd ) [2] v lcdin 25 2469.5 823.4 v lcdin 26 2399.5 823.4 v lcdin 27 2329.5 823.4 v lcdin 28 2259.5 823.4 v lcdin 29 2189.5 823.4 v lcdin 30 2119.5 823.4 res 31 1979.5 823.4 external reset input (active low) [4] v dd3 32 1699.5 823.4 supply voltage 3 [5] v dd3 33 1629.5 823.4 v dd3 34 1559.5 823.4 v dd2 35 1279.5 823.4 supply voltage 2 [5] v dd2 36 1209.5 823.4 v dd2 37 1139.5 823.4 v dd2 38 1069.5 823.4 v dd2 39 999.5 823.4 v dd2 40 929.5 823.4 v dd2 41 859.5 823.4 v dd2 42 789.5 823.4 v dd1 43 649.5 823.4 supply voltage 1 [5] v dd1 44 579.5 823.4 v dd1 45 509.5 823.4 v dd1 46 439.5 823.4 v dd1 47 369.5 823.4 v dd1 48 299.5 823.4 v dd1 49 229.5 823.4 sda 50 19.5 823.4 serial data line input of the i 2 c-bus sda 51 ? 50.5 823.4 sdack 52 ? 400.5 823.4 serial data acknowledge output [6] -53 ? 750.5 823.4 dummy sa0 54 ? 820.5 823.4 i 2 c-bus slave address input; bit 0 enr 55 ? 1100.5 823.4 enable internal power-on reset (por) input [7] table 5. bonding pad description ?continued all x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see figure 2 ). symbol pad x ( m) y ( m) description
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 8 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver t4 56 ? 1380.5 823.4 test input 4 [8] v ss2 57 ? 1660.5 823.4 ground 2 [9] v ss2 58 ? 1730.5 823.4 v ss2 59 ? 1800.5 823.4 v ss2 60 ? 1870.5 823.4 v ss2 61 ? 1940.5 823.4 v ss2 62 ? 2010.5 823.4 v ss2 63 ? 2080.5 823.4 v ss1 64 ? 2220.5 823.4 ground 1 [9] v ss1 65 ? 2290.5 823.4 v ss1 66 ? 2360.5 823.4 v ss1 67 ? 2430.5 823.4 v ss1 68 ? 2500.5 823.4 v ss1 69 ? 2570.5 823.4 v ss1 70 ? 2640.5 823.4 t3 71 ? 2780.5 823.4 test 3 [8] t1 72 ? 3060.5 823.4 test 1 [8] scl 73 ? 3410.5 823.4 serial clock line input of the i 2 c-bus scl 74 ? 3480.5 823.4 -75 ? 3830.5 823.4 dummy -76 ? 4180.5 823.4 -77 ? 4530.5 823.4 t2 78 ? 4600.5 823.4 test 2 output [10] -79 ? 4880.5 823.4 dummy -80 ? 4950.5 823.4 -81 ? 5230.5 823.4 -82 ? 5300.5 823.4 -83 ? 5650.5 823.4 -84 ? 5720.5 823.4 -85 ? 5930.5 823.4 -86 ? 5926.4 ? 821.7 r0 87 ? 5786.4 ? 821.7 lcd row driver output r2 88 ? 5716.4 ? 821.7 r4 89 ? 5646.4 ? 821.7 r6 90 ? 5576.4 ? 821.7 r8 91 ? 5506.4 ? 821.7 r10 92 ? 5436.4 ? 821.7 table 5. bonding pad description ?continued all x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see figure 2 ). symbol pad x ( m) y ( m) description
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 9 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver r12 93 ? 5366.4 ? 821.7 lcd row driver output r14 94 ? 5296.4 ? 821.7 r16 95 ? 5226.4 ? 821.7 r18 96 ? 5156.4 ? 821.7 r20 97 ? 5086.4 ? 821.7 r22 98 ? 5016.4 ? 821.7 r24 99 ? 4946.4 ? 821.7 r26 100 ? 4876.4 ? 821.7 r28 101 ? 4806.4 ? 821.7 r30 102 ? 4736.4 ? 821.7 r32 103 ? 4666.4 ? 821.7 c0 104 ? 4526.4 ? 821.7 lcd column driver output c1 105 ? 4456.4 ? 821.7 c2 106 ? 4386.4 ? 821.7 c3 107 ? 4316.4 ? 821.7 c4 108 ? 4246.4 ? 821.7 c5 109 ? 4176.4 ? 821.7 c6 110 ? 4106.4 ? 821.7 c7 111 ? 4036.4 ? 821.7 c8 112 ? 3966.4 ? 821.7 c9 113 ? 3896.4 ? 821.7 c10 114 ? 3826.4 ? 821.7 c11 115 ? 3756.4 ? 821.7 c12 116 ? 3688.4 ? 821.7 c13 117 ? 3616.4 ? 821.7 c14 118 ? 3546.4 ? 821.7 c15 119 ? 3476.4 ? 821.7 c16 120 ? 3406.4 ? 821.7 c17 121 ? 3336.4 ? 821.7 c18 122 ? 3266.4 ? 821.7 c19 123 ? 3196.4 ? 821.7 c20 124 ? 3126.4 ? 821.7 c21 125 ? 3056.4 ? 821.7 c22 126 ? 2986.4 ? 821.7 c23 127 ? 2916.4 ? 821.7 c24 128 ? 2846.4 ? 821.7 c25 129 ? 2776.4 ? 821.7 c26 130 ? 2706.4 ? 821.7 c27 131 ? 2636.4 ? 821.7 table 5. bonding pad description ?continued all x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see figure 2 ). symbol pad x ( m) y ( m) description
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 10 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver c28 132 ? 2566.4 ? 821.7 lcd column driver output c29 133 ? 2496.4 ? 821.7 c30 134 ? 2426.4 ? 821.7 c31 135 ? 2356.4 ? 821.7 c32 136 ? 2216.4 ? 821.7 c33 137 ? 2146.4 ? 821.7 c34 138 ? 2076.4 ? 821.7 c35 139 ? 2006.4 ? 821.7 c36 140 ? 1936.4 ? 821.7 c37 141 ? 1866.4 ? 821.7 c38 142 ? 1796.4 ? 821.7 c39 143 ? 1726.4 ? 821.7 c40 144 ? 1656.4 ? 821.7 c41 145 ? 1586.4 ? 821.7 c42 146 ? 1516.4 ? 821.7 c43 147 ? 1446.4 ? 821.7 c44 148 ? 1376.4 ? 821.7 c45 149 ? 1306.4 ? 821.7 c46 150 ? 1236.4 ? 821.7 c47 151 ? 1166.4 ? 821.7 c48 152 ? 1096.4 ? 821.7 c49 153 ? 1026.4 ? 821.7 c50 154 ? 956.4 ? 821.7 c51 155 ? 886.4 ? 821.7 c52 156 ? 816.4 ? 821.7 c53 157 ? 746.4 ? 821.7 c54 158 ? 676.4 ? 821.7 c55 159 ? 606.4 ? 821.7 c56 160 ? 534.6 ? 821.7 c57 161 ? 466.4 ? 821.7 c58 162 ? 396.4 ? 821.7 c59 163 ? 326.4 ? 821.7 c60 164 ? 256.4 ? 821.7 c61 165 ? 186.4 ? 821.7 c62 166 ? 116.6 ? 821.7 c63 167 ? 46.4 ? 821.7 c64 168 93.6 ? 821.7 c65 169 163.6 ? 821.7 c66 170 233.6 ? 821.7 table 5. bonding pad description ?continued all x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see figure 2 ). symbol pad x ( m) y ( m) description
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 11 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver c67 171 303.6 ? 821.7 lcd column driver output c68 172 373.3 ? 821.7 c69 173 443.6 ? 821.7 c70 174 513.6 ? 821.7 c71 175 583.6 ? 821.7 c72 176 653.6 ? 821.7 c73 177 723.6 ? 821.7 c74 178 793.6 ? 821.7 c75 179 863.6 ? 821.7 c76 180 933.6 ? 821.7 c77 181 1003.6 ? 821.7 c78 182 1073.6 ? 821.7 c79 183 1143.6 ? 821.7 c80 184 1213.6 ? 821.7 c81 185 1283.6 ? 821.7 c82 186 1353.6 ? 821.7 c83 187 1423.6 ? 821.7 c84 188 1493.6 ? 821.7 c85 189 1563.6 ? 821.7 c86 190 1633.6 ? 821.7 c87 191 1703.6 ? 821.7 c88 192 1773.6 ? 821.7 c89 193 1843.6 ? 821.7 c90 194 1913.6 ? 821.7 c91 195 1983.6 ? 821.7 c92 196 2053.6 ? 821.7 c93 197 2123.6 ? 821.7 c94 198 2193.6 ? 821.7 c95 199 2263.6 ? 821.7 c96 200 2403.6 ? 821.7 c97 201 2473.6 ? 821.7 c98 202 2543.6 ? 821.7 c99 203 2613.6 ? 821.7 c100 204 2683.6 ? 821.7 c101 205 2753.6 ? 821.7 c102 206 2823.6 ? 821.7 c103 207 2893.6 ? 821.7 c104 208 2963.6 ? 821.7 c105 209 3033.6 ? 821.7 table 5. bonding pad description ?continued all x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see figure 2 ). symbol pad x ( m) y ( m) description
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 12 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver c106 210 3103.6 ? 821.7 lcd column driver output c107 211 3173.6 ? 821.7 c108 212 3243.6 ? 821.7 c109 213 3313.6 ? 821.7 c110 214 3383.6 ? 821.7 c111 215 3453.6 ? 821.7 c112 216 3523.6 ? 821.7 c113 217 3593.6 ? 821.7 c114 218 3663.6 ? 821.7 c115 219 3733.6 ? 821.7 c116 220 3803.6 ? 821.7 c117 221 3873.6 ? 821.7 c118 222 3943.6 ? 821.7 c119 223 4013.6 ? 821.7 c120 224 4083.6 ? 821.7 c121 225 4153.6 ? 821.7 c122 226 4223.6 ? 821.7 c123 227 4293.6 ? 821.7 c124 228 4363.6 ? 821.7 c125 229 4433.6 ? 821.7 c126 230 4503.6 ? 821.7 c127 231 4573.6 ? 821.7 r33 232 4713.6 ? 821.7 lcd row driver output; icon row r31 233 4783.6 ? 821.7 lcd row driver output r29 234 4853.6 ? 821.7 r27 235 4923.6 ? 821.7 r25 236 4993.6 ? 821.7 r23 237 5063.6 ? 821.7 r21 238 5113.6 ? 821.7 r19 239 5203.6 ? 821.7 r17 240 5343.6 ? 821.7 r15 241 5413.6 ? 821.7 r13 242 5483.6 ? 821.7 r11 243 5553.6 ? 821.7 r9 244 5623.6 ? 821.7 r7 245 5693.6 ? 821.7 r5 246 5763.6 ? 821.7 r3 247 5833.6 ? 821.7 r1 248 5903.6 ? 821.7 table 5. bonding pad description ?continued all x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see figure 2 ). symbol pad x ( m) y ( m) description
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 13 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver [1] if the on-chip oscillator is used, this input must be connected to v dd1 . [2] if the internal v lcd generation is used, v lcdout , v lcdin , and v lcdsense must be connected together. [3] if an external v lcd is used in the application, then pin v lcdout must be left open-circuit, otherwise the chip will be damaged. [4] if only the internal power-on reset (por) is used, this input must be connected to v dd1 . [5] v dd1 is for the logic supply, v dd2 and v dd3 are for the voltage multiplier. for split power supplies, v dd2 and v dd3 must be connected together. if only one supply voltage is available, v dd1 , v dd2 ,andv dd3 must be connected together. [6] serial data acknowledge for the i 2 c-bus. by connecting sdack to sda externally, the sda line becomes fully i 2 c-bus compatible. having the acknowledge output separated from the serial data line is advantageous in chip-on-glass (cog) applications. in co g applications where the track resistance from the sdack pad to the system sda line can be signifi cant, a potential divider is generated by the bus pull-up resistor and the indium tin oxide (ito) track re sistance. it is possible that the pcf8531 will not be able to create a valid logic 0 level during the acknowledge cycle. by spli tting the sda input from the sdack output, the device could be used in a mode that i gnores the acknowledge bit. in cog applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the sdack pad to the system sda line to guarantee a valid low level. [7] if enr is connected to v ss , power-on reset (por) is disabled; to enable power-on reset (por) enr must be connected to v dd1 . [8] in the application, this input must be connected to v ss . [9] v ss1 and v ss2 must be connected together. [10] in the application, t2 must be left open-circuit.
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 14 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver 7. functional description 7.1 oscillator the on-chip oscillator provides the clock signal for the di splay system. no external components are required and the osc input must be connected to v dd . an external clock signal, if used, is connected to this input. 7.2 power-on reset (por) the on-chip power-on reset (por) initializes the chip after power-on or power failure. 7.3 i 2 c-bus controller the i 2 c-bus controller receives and executes the commands. the pcf8531 acts as an i 2 c-bus slave receiver and therefore it cannot control bus communication. 7.4 input filters to enhance noise immunity in electrically ad verse environments, rc low-pass filters are provided on the sda and scl lines. 7.5 display data ram the pcf8531 contains 34 128 bits static ram for storing the display data, see figure 7 . the ram is divided into 6 banks of 128 bytes (6 8 128 bits). bank 5 is used for icon data. during ram access, data is transferred to the ram via the i 2 c-bus interface. there is a direct correspondence between the x address and column output number. 7.6 timing generator the timing generator produces the various sig nals required to drive the internal circuitry. internal chip operation is not affected by operations on the data buses. 7.7 address counter the address counter sets the addresses of the display data ram for writing. 7.8 display address counter the display address counter generates the addresses for read out of the display data. 7.9 command decoder the command decoder identifies command words that arrive on the i 2 c-bus and determines the destination for the following data bytes.
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 15 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver 7.10 bias voltage generator the bias voltage generator generates four buffered intermediate bias voltages. this block contains the generator for the reference volt ages and the four buffers. this block can operate in two voltage ranges: ? normal mode: 4.0 v to 9.0 v ? power save mode: 3.0 v to 9.0 v. 7.11 v lcd generator the v lcd voltage generator contains a configurable 2 to 5 times voltage multiplier; this is programmed by software. 7.12 reset the pcf8531 has the possibility of two reset modes: internal power-on reset (por) or external reset (res ). the reset mode is selected usi ng the enr signal. after a reset, the chip has the following state: ? all row and column outputs are set to v ss (display off) ? ram data is undefined ? power-down mode 7.13 power-down during power-down, all static currents are switched off (no internal oscillator, no timing and no lcd segment drive system) and all lcd outputs are internally connected to v ss . the i 2 c-bus function remains operational. 7.14 column driver outputs the lcd drive section includes 128 colu mn outputs (c0 to c127) which must be connected directly to the lcd. the column output signals are generated in accordance with the multiplexed row signals and with the data in the display latch. when less than 128 columns are required, the unused colu mn outputs must be left open-circuit. 7.15 row driver outputs the lcd drive section includes 34 row outputs (r0 to r33), which must be connected directly to the lcd. the row output signals are generated in accordance with the selected lcd drive mode. if less than 34 rows or lowe r multiplex rates are required, the unused outputs must be left open-circuit. the row sign als are interlaced i.e. the selection order is r0,r2,...,r1,r3,etc.
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 16 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver 8. lcd waveforms and ddram to data mapping the lcd waveforms and the ddram to display data mapping are shown in figure 5 , figure 6 and figure 7 . (1) v state1 (t) = c1(t) ? r0(t). (2) v state2 (t) = c1(t) ? r1(t). fig 5. typical lcd driver waveforms mgs466 row 0 r0(t) row 1 r1(t) col 0 c0(t) col 1 c1(t) 0 v 0 v v 3 ? v ss frame n frame n + 1 02468... 1357... ... 33 ... 32 0 2 4 6 8... 1 3 5 7... ... 33 ... 32 v state1 (t) v state1 (t) v state2 (t) v lcd v 2 v 3 v 4 v 5 v ss v lcd v 2 v 3 v 4 v 5 v ss v lcd v 2 v 3 v 4 v 5 v ss v lcd v 2 v 3 v 4 v 5 v ss v lcd v lcd ? v 2 v 4 ? v 5 v ss ? v 5 v 4 ? v lcd v 3 ? v 2 ? v lcd 0 v 0 v v 3 ? v ss v state2 (t) v lcd v lcd ? v 2 v 4 ? v 5 v 4 ? v lcd v 3 ? v 2 v ss ? v 5 ? v lcd
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 17 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver fig 6. lcd waveforms, icon mode, multiplex rate 1:2 mgs467 row 0 to 32 row 33 col 1 on/off col 2 off/on col 3 on/on col 4 off/off frame n frame n + 1 v lcd v 2 v 3 v 4 v 5 v ss v lcd v 2 v 3 v 4 v 5 v ss v lcd v 2 v 3 v 4 v 5 v ss v lcd v 2 v 3 v 4 v 5 v ss v lcd v 2 v 3 v 4 v 5 v ss v lcd v 2 v 3 v 4 v 5 v ss only icons are driven
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 18 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver 8.1 addressing data is written in bytes into the ram matrix of the pcf8531 as shown in figure 8 , figure 9 and figure 10 . the display ram has a matrix of 34 128 bits. the columns are addressed by the address pointer. the address ranges are x 0 to x 127 (7fh) and y 0 to y 5 (5h). addresses outside of these ranges are not allowed. in vertical addressing mode (v = 1), the y address increments after each byte (see figure 9 ). after the last y address (y = 4), y wraps around to 0 and x increments to address the next column. in horizontal addressing mode (v = 0), the x address increments after each byte (see figure 10 ). after the last x address (x = 127), x wraps around to 0 and y increments to address the next fig 7. ddram to display data mapping top of lcd mgs468 bank 0 bank 1 bank 2 bank 3 bank 4 r32 r24 r16 r8 r0 r33 (icon row) bank 5 lcd ddram
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 19 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver row. after the very last address (x = 127 and y = 4), the address pointers wrap around to address (x = 0 and y = 0). the y address 5 is reserved for icon data and is not affected by the addressing mode. please note that in bank 4 only the lsb (db0) of the data is written into the ram and in bank 5 only the 5th data bit (db4) is written into the ram. fig 8. ram format and addressing mgs46 9 0 1 2 3 5 4 0 127 x address icon data y address lsb msb lsb msb lsb msb fig 9. sequence of writing data bytes into ram with vertical addressing (v = 1) mgs470 05 16 2 3 4 0 1 icon data 638 639 0 127 x address y address 0 1 2 3 4 5 fig 10. sequence of writing data bytes into ram with horizontal addressing (v = 0) mgs471 012 128 129 130 256 257 258 384 385 386 512 513 514 0 1 icon data 0 1 2 3 4 5 127 255 383 511 639 0 127 x address y address
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 20 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver 9. instructions only two pcf8531 registers, the instruction re gister and the data register can be directly controlled by the mpu. before internal operati on, control information is stored temporarily in these registers to allow interfacing to vari ous types of mpus which operate at different speeds or to allow interfacing to peripheral control ics. the pcf8531 operation is controlled by the inst ructions given in ta b l e 11 . instructions are of four types: ? those that define pcf8531 functions e.g. display configuration, etc. ? those that set internal ram addresses ? those that perform data transfer to/from the internal ram ? others in normal mode instructions which perform data transfer to/from the internal ram are used most frequently. automatic incrementing by 1 of internal ram addresses after each data write reduces the mpu program load. 9.1 reset after reset or internal power-on reset (por) (depending on the application), the lcd driver is set to the following state: ? power-down mode (pd = 1) ? horizontal addressing (v = 0) ? display blank (d = 0; e = 0), no icon mode (im = 0) ? address counter x[6:0] = 0; y[2:0] = 0 ? bias system bs[2:0] = 0 ? multiplex rate m[1:0] = 0 (multiplex rate 1:17) ? temperature control mode tc[2:0] = 0 ? hv-gen control, hve = 0 the high voltage (hv) generator is switched off, prs = 0 and s[1:0] = 0 ? v lcd =0v ? ram data is undefined ? command page definition h[1:0] = 0
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 21 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver 9.2 function set 9.2.1 pd when pd = 1, the power-down mode of the lcd driver is active: ? all lcd outputs at v ss (display off) ? power-on reset (por) detect ion active, oscillator off ? v lcd can be disconnected ? i 2 c-bus is operational, commands can be executed ? ram contents not cleared; ram data can be written ? register settings remain unchanged 9.2.2 v when v = 0 the horizontal addressing is sele cted. the data is written into the ddram as shown in figure 10 . when v = 1 the vertical addressing is selected. the data is written into the ddram as shown in figure 9 . icon data is written independently of v when y address is 5. 9.3 set y address bits y2, y1, and y0 define the y address vector of the display ram (see ta b l e 6 ). 9.4 set x address the x address points to the columns. the range of x is 0 to 127 (7fh). 9.5 set multiplex rate m[1:0] selects the multiplex rate (see ta b l e 7 ). 9.6 display control (d, e, and im) bits d and e select the display mode (see ta b l e 1 3 ). bit im (see table 12 ) sets the display to icon mode. table 6. y address y2 y1 y0 bank 0000 0011 0102 0113 1004 1015 (icons) table 7. multiplex rates multiplex rate m1 m0 1:17 0 0 1:26 1 0 1:34 0 1
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 22 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver 9.7 set bias system the bias voltage levels are set in the ratio of r ? r ? n r ? r ? r (see figure 11 ). different multiplex rates require different bias settings. bias settings are programmed by bs[2:0], which sets the binary number n. the optimum value for n is given by: supported values of n are given in table 8 . ta b l e 9 shows the intermediate bias voltages. fig 11. voltage divider chain table 8. programming the required bias system bs[2:0] n bias system comment 000 7 1 ? 11 - 001 6 1 ? 10 - 010 5 1 ? 9 - 011 4 1 ? 8 - 100 3 1 ? 7 recommended for 1:34 101 2 1 ? 6 recommended for 1:26 110 1 1 ? 5 recommended for 1:17 111 0 1 ? 4 recommended for icon mode r r r n r r v 6 = v ss v 5 v 4 v 3 v 2 v 1 = v lcd 013aaa183 nmuxrate3 ? =
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 23 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver 9.8 lcd bias voltage 9.9 set v lcd value v lcd can be set by software. the voltage at intersection temperature [v lcd (t = t ints )] can be calculated as: v lcd (t ints )=a+v lcd b the generated voltage is dependent on the temperature, programmed temperature coefficient (tc) and the programmed voltage at intersection temperature (t ints ). v lcd = v lcd (t ints ) [1 + tc (t ? t ints )] the parameter values are given in ta b l e 1 0 . two overlapping v lcd ranges can be selected via the command hv-gen control (see ta b l e 1 0 and figure 12 ). the maximum voltage which can be generated depends on the v dd2 and v dd3 voltages and the display load current. for multiplex rate 1:34, the optimum v lcd can be calculated as: where v th is the threshold voltage of the liquid crystal material used. the practical value for v lcd is determined by equating v off(rms) with a defined lcd threshold voltage (v th ), typically when the lcd exhi bits approximately 10 % contrast. as the programming range for the internally generated v lcd allows values above the maximum allowed v lcd , the user must ensure, while setting the vop register and selecting the temperature compensation, that the v lcd limit maximum of 9.0 v is never exceeded under all conditions and including all tolerances. table 9. intermediate lcd bias voltages symbol bias voltage example for 1 ? 7 bias v1 v lcd v lcd v2 6 ? 7 v lcd v3 5 ? 7 v lcd v4 2 ? 7 v lcd v5 1 ? 7 v lcd v6 v ss v ss n3 + n4 + ----------- - v lcd n2 + n4 + ----------- - v lcd 2 n4 + ----------- - v lcd 1 n4 + ----------- - v lcd v lcd 134 + 21 1 34 --------- - ? ?? ?? ------------------------------------- - v th 5.30 v th ==
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 24 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver 9.10 voltage multiplier control s[1:0] the pcf8531 incorporates a software configurable voltage multiplier. after reset (internal or external), the voltage multiplier is set to 2 v dd2 . the voltage multip lier factors are set by setting bits s[1:0] (see ta b l e 1 3 ). 9.11 temperature compensation due to the temperature dependency of the viscosity of the liquid crystals, the lcd controlling voltage v lcd should usually be increased at lower temperatures to maintain optimum contrast. figure 13 shows v lcd for high multiplex rates. table 10. parameter values for the hv generator programming symbol value unit prs = 0 prs = 1 t ints 27 27 c a 2.94 6.75 v b 0.03 0.03 v programming range 2.94 to 6.75 6.75 to 10.56 v vop[6:0] (programmed) [00h to 7fh] program range low to high. fig 12. v lcd programming of pcf8531 mgl935 00 01 02 a v lcd 03 04 05 06 . . . 7d 7e 7f 00 01 02 03 04 05 06 . . . 5f 6f 7f b low high
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 25 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver linear temperature compensation is supported in the pcf8531. the temperature coefficient of v lcd can be selected from eight values by setting bits tc[2:0] (see ta b l e 1 3 ). fig 13. v lcd as a function of liquid crystal temperature mgs473 t v lcd 0 c table 11. instruction set instruction i 2 c-bus command [1] i 2 c-bus command byte description rs r/w db7 db6 db5 db4 db3 db2 db1 db0 h1 and h0 = don?t care (h independent command page) nop 0000000000no operation write data 1 0 d7d6d5d4d3d2d1d0write data to display ram set default h[1:0]0000000001select h[1:0] = 0 h1 = 0 and h0 = 0 (function and ram command page) instruction set 0 0 0 0 0 0 1 0 h1 h0 select command page function set 0 0 0 0 1 0 0 pd v 0 power-down control; entry mode set y address of ram 0 0 0 1 0 0 0 y2 y1 y0 set y address of ram; 0 y 5 set x address of ram 0 0 1 x6 x5 x4 x3 x2 x1 x0 set x address of ram; 0 x 127 h1 = 0 and h0 = 1 (display setting command page) multiplex rate 0 0 0 0 0 0 0 1 m1 m0 set multiplex rate display control 00000 0 1 d im e set display configuration bias system 0 0 0 0 0 1 0 bs2 bs1 bs0 set bias system (bsx) h1 = 1 and h0 = 0 (hv-gen command page) hv-gen control00000001prshveset v lcd programming range hv-gen configuration 00000010s1s0set voltage multiplication factor
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 26 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver [1] r/w is set to the slave address byte; co and rs are set in the control byte. [1] the bits h[1:0] identify the command page (use set default h[1:0] command to set h[1:0] = 0). temperature control 0 0 0 0 1 0 0 tc2 tc1 tc0 set temperature coefficient test modes 0 0 0 1 xxxxxxdo not use (reserved for test) v lcd control 0 0 1 vop6 vop5 vop4 vop3 vop2 vop1 vop0 set v lcd register table 11. instruction set ?continued instruction i 2 c-bus command [1] i 2 c-bus command byte description rs r/w db7 db6 db5 db4 db3 db2 db1 db0 table 12. explanation for symbols in table 11 bit 0 1 pd chip is active chip is in power-down mode v horizontal addressing vertical addressing im normal mode; full display + icons icon mode; only icons are displayed h[1:0] [1] see table 13 d and e see table 13 hve voltage multiplier disabled voltage multiplier enabled prs v lcd programming range low v lcd programming range high tc[2:0] see table 13 s[1:0] see table 13 table 13. description of bits h, d and e, tc and s bits value description command page (h) h[1:0] 00 function and ram command page 01 display setting command page 10 hv-gen command page display modes (d, e) d and e 00 display blank 10 normal mode 01 all display segments 11 inverse video mode
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 27 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver temperature coefficient (tc) tc[2:0] 000 temperature coefficient tc 0 001 temperature coefficient tc 1 010 temperature coefficient tc 2 011 temperature coefficient tc 3 100 temperature coefficient tc 4 101 temperature coefficient tc 5 110 temperature coefficient tc 6 111 temperature coefficient tc 7 voltage multiplier factor (s) s[1:0] 00 2 voltage multiplier 01 3 voltage multiplier 10 4 voltage multiplier 11 5 voltage multiplier table 13. description of bits h, d and e, tc and s ?continued bits value description
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 28 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver 10. i 2 c-bus interface 10.1 characteristics of the i 2 c-bus the i 2 c-bus is for bidirectional, two-line commun ication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor. data transfer may be initiated only when the bus is not busy. 10.1.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see figure 14 ). 10.1.2 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, wh ile the clock is high is defin ed as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p). the start and stop conditions are shown in figure 15 . 10.1.3 system configuration the system configuration is shown in figure 16 . ? transmitter: the device that sends the data to the bus ? receiver: the device that rece ives the data from the bus ? master: the device that initiates a transfer , generates clock signals and terminates a transfer ? slave: the device addressed by a master fig 14. bit transfer mbc62 1 data line stable; data valid change of data allowed sda scl fig 15. definition of start and stop conditions mbc62 2 sda scl p stop condition sda scl s start condition
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 29 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver ? multi-master: more than one master can atte mpt to control the bus at the same time without corrupting the message ? arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted ? synchronization: procedure to synchronize t he clock signals of two or more devices. 10.1.4 acknowledge the number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlim ited. each byte of eight bits is followed by an acknowledge cycle. ? a slave receiver which is addressed must generate an acknowledge after the reception of each byte. ? also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. ? the device that acknowledges must pull-down the sda line during the acknowledge clock pulse, so that the sda line is st able low during the high period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). ? a master receiver must signal an end of da ta to the transmitter by not generating an acknowledge on the last byte that has been cl ocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition. acknowledgement on the i 2 c-bus is shown in figure 17 . fig 16. system configuration mga80 7 sda scl master transmitter/ receiver master transmitter slave transmitter/ receiver slave receiver master transmitter/ receiver
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 30 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver 10.2 i 2 c-bus protocol this driver does not support read. the pcf8531 is a slave receiver. therefore, it only responds when r/w = 0 in the slave address byte. before any data is transmitted on the i 2 c-bus, the device that must respond is addressed first. two 7-bit slave addresses (0111100 an d 0111101) are reserved for the pcf8531. the least significant bit of the slave address is set by connecting the input sa0 to either logic 0 (v ss ) or logic 1 (v dd ). the i 2 c-bus protocol is shown in figure 18 . the sequence is initiated with a start condition (s) from the i 2 c-bus master, and is followed by the slave address. all slaves with the corresponding address acknowledge in parallel, all othe rs ignore the i 2 c-bus transfer. after acknowledgement, one or more command words follow, which define the stat us of the addressed slaves. a command word consists of a control byte, which defines co and rs, plus a data byte (see figure 19 and table 11 ). the last control byte is tagged with a cleared most significant bit, the continuation bit co. the control and data bytes are also acknowledged by all addressed slaves on the bus. after the last control byte, depending on the rs bit setting, either a series of display data bytes or command data bytes may follow. if the rs bit was set logic 1, these display bytes are stored in the display ram at the address specified by the data pointer. the data pointer is automatically updated and the data is directed to the intended pcf8531 device. if the rs bit of the last control byte was set logic 0, these command bytes will be decoded and the setting of t he device will be changed according to the received commands. the acknowledgement after each byte is made only by the addressed pcf8531. at the end of the transmission, the i 2 c-bus master issues a stop condition (p). fig 17. acknowledge on the i 2 c-bus mbc60 2 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 31 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver 10.3 command decoder the command decoder identifies command words that arrive on the i 2 c-bus. the most significant bit of a control byte is the continuation bit co. if th is bit is logic 1, it indicates that only one data byte (eit her command or ram data) will follo w. if this bit is logic 0, it indicates that a series of data bytes (either command or ram data) may follow. the db6 bit of a control byte is the ram data/command bit rs. when this bit is logic 1, it indicates that another ram data byte will be transferred next. if the bit is logic 0, it indicates that another command byte will be transferred next. ? pairs of bytes; information in the seco nd byte, the first byte determines whether information is displa y or instruction data ? stream of information bytes after co = 0; disp lay or instruction da ta, depending on last rs. fig 18. slave address and control byte mgs47 4 s011110sa0 a slave address r/w corsxxxxxx control byte fig 19. master transmits to slave receiver; write mode mgs475 s011110 s a 0 0a acknowledge from pcf8531 acknowledge from pcf8531 acknowledge from pcf8531 acknowledge from pcf8531 acknowledge from pcf8531 1 control byte a data byte data byte n 0 bytes 1 byte slave address msb . . . . . . . . . . . lsb 2n 0 bytes a co co 0a ap rs r/w control byte rs
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 32 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver 11. internal circuitry for all diagrams the maximum forward current is 5 ma and the maximum reverse voltage is 5 v. fig 20. device protection diagrams mgs485 v dd1 v dd1 v ss1 v ss2 v ss1 scl, sda, sdack v ss1 v lcdin v ss1 v ss1 v dd1 osc, sa0, t3, t1, t4, res, enr v ss1 v dd1 t2 pads 43 to 49 pads 35 to 42 pads 57 to 63 v dd3 v ss1 pads 32 to 34 v lcdout v ss1 pads 17 to 23 v lcdin (supply), v lcdsense v ss1 pads 16, 24 to 30 pads 87 to 248 pads 73, 74, 50, 51, 52 pads 15, 54, 71, 72, 56, 31, 55 pad 78 pads 64 to 70 pads 57 to 63 v dd2 v ss1 v ss2
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 33 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver 12. limiting values [1] parameters are valid over the whole operating tem perature range unless otherwise specified. all voltages are referenced to v ss unless otherwise specified. [2] pass level; human body model (hbm), according to ref. 6 ? jesd22-a114 ? . [3] pass level; machine model (mm), according to ref. 7 ? jesd22-a115 ? . [4] pass level; latch-up testing according to ref. 8 ? jesd78 ? at maximum ambient temperature (t amb(max) ). [5] according to the nxp store and transport requirements (see ref. 10 ? nx3-00092 ? ) the devices have to be stored at a temperature of +8 c to +45 c and a humidity of 25 % to 75 %. for long term storage products deviant conditions are described in that document. table 14. limiting values [1] in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd1 supply voltage 1 logic supply ? 0.5 +5.5 v v dd2 supply voltage 2 multiplier supply ? 0.5 +4.5 v v dd3 supply voltage 3 multiplier supply ? 0.5 +4.5 v v lcd lcd supply voltage ? 0.5 +9.0 v v i input voltage ? 0.5 v dd + 0.5 v v o output voltage ? 0.5 v dd + 0.5 v i dd(lcd) lcd supply current ? 50 +50 ma i ss ground supply current ? 50 +50 ma i i input current ? 10 +10 ma i o output current ? 10 +10 ma p tot total power dissipation - 300 mw p/out power dissipation per output - 30 mw v esd electrostatic discharge voltage hbm [2] - 1500 v mm [3] - 200 v i lu latch-up current [4] -200 ma t j junction temperature - +150 c t stg storage temperature [5] ? 65 +150 c t amb ambient temperature operating device ? 40 +85 c
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 34 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver 13. static characteristics table 15. static characteristics v dd1 = 1.8 v (1.9 v) to 5.5 v; v dd2 and v dd3 = 2.5 v to 4.5 v; v ss1 = v ss2 =0v; v dd1 to v dd3 v lcd 9.0 v; t amb = ? 40 cto+85 c; unless otherwise specified. symbol parameter conditions min typ max unit supplies v lcd lcd supply voltage [1] 4.0 - 9.0 v icon mode [1] 3.0 - 9.0 v v dd1 supply voltage 1 logic supply 1.9 - 5.5 v t amb ? 25 c1.8-5.5v v dd2 supply voltage 2 multiplier supply; lcd voltage internally generated 2.5 - 4.5 v v dd3 supply voltage 3 multiplier supply; lcd voltage internally generated 2.5 - 4.5 v i dd supply current power-down mode; internal v lcd -210 a normal mode; internal v lcd [2] [3] - 170 350 a normal mode; external v lcd [2] -1050 a i dd(lcd) lcd supply current normal mode; external v lcd [2] [4] -25100 a icon mode; external v lcd [2] [5] -1570 a v por power-on reset voltage [6] 0.9 1.2 1.6 v logic v il low-level input voltage v ss -0.3v dd v v ih high-level input voltage 0.7v dd -v dd v i ol(sda) low-level output current on pin sda v ol = 0.4 v; v dd = 5.0 v 3.0 - - ma i li input leakage current v i = v dd or v ss ? 1- +1 a column and row outputs r o output resistance column outputs: c0 to c127 [7] -1220k row outputs: r0 to r33 - 12 20 k v bias bias voltage variation outputs r0 to r33 and c0 to c127 ? 100 0 +100 mv v lcd lcd voltage variation tc 1 to tc 7 [8] -- 3.9 % tc temperature coefficient t amb = ? 20 c to +70 c tc 0 ; tc[2:0] = 000 - 0 - %/k tc 1 ; tc[2:0] = 001 - ? 0.026 - %/k tc 2 ; tc[2:0] = 010 - ? 0.039 - %/k tc 3 ; tc[2:0] = 011 - ? 0.052 - %/k tc 4 ; tc[2:0] = 100 - ? 0.078 - %/k tc 5 ; tc[2:0] = 101 - ? 0.13 - %/k tc 6 ; tc[2:0] = 110 - ? 0.19 - %/k tc 7 ; tc[2:0] = 111 - ? 0.26 - %/k t ints intersection temperature - 27 - c
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 35 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver [1] as the programming range for the internally generated v lcd allows values above the maximum allowed v lcd , the user must ensure, while setting the vop register and selecting the temperature compensation, that the v lcd maximum limit of 9 v will never be exceeded under all conditions and including all tolerances. [2] lcd outputs are open circuit, inputs at v dd or v ss ; bus inactive. [3] v dd1 to v dd3 = 2.85 v; v lcd = 7.0 v; voltage multiplier = 3 v dd ; f osc =34khz. [4] v dd1 to v dd3 = 2.75 v; v lcd = 9.0 v; f osc =34khz. [5] v dd1 to v dd3 = 2.75 v; v lcd = 3.5 v; f osc =34khz. [6] resets all logic when v dd1 < v por . [7] i load 50 a; outputs are tested one at a time. [8] v lcd 7.7 v. 14. dynamic characteristics [1] f fr =f clk(ext) /480 or f osc /480. [2] a reset is generated if t w(resl) > 3ns (see figure 21 ). [3] all timing values are valid within the operating supply voltage and ambient temperature range and are referenced to v il and v ih , with an input voltage swing of v ss to v dd . [4] c b = total capacitance of one bus line in pf. table 16. dynamic characteristics v dd1 = 1.8 v (1.9 v) to 5.5 v; v dd2 and v dd3 = 2.5 v to 4.5 v; v ss1 = v ss2 =0v; v dd1 to v dd3 v lcd 9.0 v; t amb = ? 40 cto+85 c; unless otherwise specified. symbol parameter conditions min typ max unit f fr(lcd) lcd frame frequency v dd = 3.0 v [1] 40 66 135 hz f osc oscillator frequency 20 34 65 khz f clk(ext) external clock frequency 20 - 65 khz t w(resl) res low pulse width [2] 300 - - ns t su(resl) res low set-up time - - 30 s serial bus interface (see figure 22 ) [3] f scl scl clock frequency 0 - 400 khz t low low period of the scl clock 1.3 - - s t high high period of the scl clock 0.6 - - s t su;dat data set-up time 100 - - ns t hd;dat data hold time 0 - 0.9 ns t r rise time of both sda and scl signals [4] 20 + 0.1c b -0.3 s t f fall time of both sda and scl signals [4] 20 + 0.1c b -0.3 s c b capacitive load for each bus line - - 400 pf t su;sta set-up time for a repeated start condition 0.6 - - s t hd;sta hold time (repeated) start condition 0.6 - - s t su;sto set-up time for stop condition 0.6 - - s t sp pulse width of spikes that must be suppressed by the input filter on bus - - 50 ns t buf bus free time between a stop and start condition 1.3 - - s
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 36 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver fig 21. reset timing mgs4 76 t w(resl) t su(resl) v il v dd res fig 22. i 2 c-bus timing sda mga72 8 sda scl t su;sta t su;sto t hd;sta t buf t low t hd;dat t high t r t f t su;dat
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 37 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver v dd1 =2v; 4 voltage multiplier; t amb =27 c; tc = 0; bs = 100; no v lcd load. v dd1 = 1.8 v; v dd2 and v dd3 = 2.6 v; t amb =27 c; f osc =34khz; nov lcd load. fig 23. supply current as a function of supply voltage 2 and supply voltage 3 fig 24. supply current as a function of lcd supply voltage; different multiplication factors 23 4 5 400 200 100 300 mgs477 i dd ( a) v dd2 and v dd3 (v) 4 v v lcd = 9 v 7.5 v 246 10 400 200 100 300 mgs478 8 i dd ( a) v lcd (v) 2 5 4 3 v lcd = 7.5 v; v dd1 to v dd3 = 2.7 v; t amb =27 c; no v lcd load. v dd1 = 1.8 v; v dd2 and v dd3 = 2.5 v; external v lcd ; t amb =27 c; tc = 0; bs = 100; no v lcd load. fig 25. lcd supply voltage as a function of temperature fig 26. supply current as a function of lcd supply voltage ? 50 0 50 100 9 7 6 8 mgs479 tc 0 tc 1 tc 6 v lcd (v) t ( c) tc 7 246 10 30 10 0 20 mgs480 8 i ( a) v lcd (v) i dd i dd(lcd)
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 38 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver v dd1 = 2.5 v; v dd2 and v dd3 = 2.5 v; external v lcd ; t amb =27 c; tc = 0; bs = 100; no v lcd load. v dd1 = 1.8 v; v dd2 = 2.5 v; 2 voltage multiplier; t amb =27 c; tc = 0; bs = 111; no v lcd load. fig 27. supply current as a function of frequency fig 28. supply current as a function of lcd supply voltage 02040 80 30 10 0 20 mgs481 60 i ( a) f (khz) i dd i dd(lcd) 3 86 82 84 80 78 3.2 4 mgs482 3.4 3.6 3.8 i dd ( a) v lcd (v)
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 39 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver 15. application information 15.1 typical system configuration the host microprocessor/microcontroller and the pcf8531 are both connected to the i 2 c-bus. the sda and scl lines must be connected to the positive power supply via pull-up resistors. the internal oscillator requires no external component s. the appropriate intermediate biasing voltage for the multiplexed lcd waveforms are generated on-chip. the only other connections required to co mplete the syste m are to the power supplies (v dd , v ss , and v lcd ) and suitable capacitors for decoupling v lcd and v dd . 15.2 power supply connections for internal v lcd generation fig 29. typical system configuration mgs483 host microprocessor/ microcontroller lcd panel sda v ss1 , v ss2 v ss v dd(i2c) v lcd v dd1 to v dd3 v ss1 , v ss2 scl sda scl sa0 pcf8531 res sdack r pu r pu res enr 128 column drivers 34 row drivers fig 30. recommended v dd connections for internal v lcd generation v dd1 v dd2 v dd3 v ss1 v ss2 gnd 1.8 v (1.9 v) to 5.5 v 2.5 v to 4.5 v 013aaa35 4 1 f 1 f v dd1 v dd2 v dd3 v ss1 v ss2 gnd 2.5 v to 4.5 v 013aaa35 5 1 f
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 40 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver 15.3 power supply connections for external v lcd generation 15.4 information about v lcd connections v lcdin ? this input is used for generating the 5 lcd bias levels. it is the power supply for the bias level buffers. v lcdout ? this is the v lcd output if v lcd is generated internally. it is the output of the charge pump. in this case pin v lcdout must be connected to v lcdin and to v lcdsense (see figure 31 ). v lcdout must be left open circuit when v lcd is supplied from an external source (see figure 32 ). v lcdsense ? when using the internal v lcd generation, this pin must be connected to v lcdout and v lcdin (see figure 31 ). when using an external v lcd supply it must be connected to v lcdin or to ground (see figure 32 ). fig 31. recommended v lcd connections for internal v lcd generation 013aaa35 6 v ss2 v lcdin v lcdout v lcdsense 1 f remark: when using an external v lcd , the internal v lcd generator must never be switched on otherwise damages will occur. fig 32. recommended v dd connections for external v lcd generation 013aaa35 8 v lcdin v lcdout v lcdsense n.c. 4.0 v to 9.0 v 1 f or v lcdin v lcdout v lcdsense n.c. 4.0 v to 9.0 v v dd1 v dd2 v dd3 v ss1 v ss2 gnd 1.8 v (1.9 v) to 5.5 v 1 f
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 41 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver 15.5 chip-on-glass application the required minimum values for the external capacitors in a chip-on-glass application are: ? c ext = 100 nf between v lcd and v ss1, v ss2 ; c ext = 470 nf between v dd1 , v dd2 , v dd3 and v ss1 , v ss2 . ? higher capacitor values are recommended for ripple reduction. ? for cog applications, the recommended ito track resistance must be minimized for the i/o and supply connections. optimized values for these tracks are below 50 for the supply (r supply ) and below 100 for the i/o connections (r i/o ). ? to reduce the sensitivity of the reset to esd/emc disturbances for a cog application, nxp strongly recommended implementing a series input resistance in the reset line (recommended minimum value 8 k ) on the glass (ito). if the reset input is not used, this input must be connected to v dd1 using a short connection. fig 33. chip-on-glass application mgs48 4 3 display 34 128 pixels v dd1 to v dd3 i/o v ss1 v ss2 c ext r supply r i/o v lcd pcf8531 128 17 17
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 42 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver 15.6 programming example table 17. programming example for pcf8531 step serial bus byte display operation db7 db6 db5 db4 db3 db2 db1 db0 1 011110sa00 start; slave address; r/w =0 2 10000000 control byte; co=1; rs=0 3 00000001 h[1:0] indepe ndent command; select function and ram command page (h[1:0] = 00) 4 10000000 control byte; co=1; rs=0 5 00100010 function and ram command page pd = 0 and v = 1 6 10000000 control byte; co=1; rs=0 7 00001001 function and ram command page select display setting command page h[1:0] = 01 8 10000000 control byte; co=1; rs=0 9 00001100 display setting command page; set normal mode (d = 1; im = 0 and e = 0) 10 10000000 control byte; co=1; rs=0 11 00000101 select multiplex rate 1:34 12 10000000 control byte; co=1; rs=0 13 00000001 h[2:0] indepe ndent command; select function and ram command page h[1:0] = 00 14 10000000 control byte; co=1; rs=0 15 00001010 function and ram command page; select hv-gen command page h[1:0] = 10 16 10000000 control byte; co=1; rs=0 17 00001011 hv-gen command page; select voltage multiplication factor 5 s[1:0] = 11 18 10000000 control byte; co=1; rs=0 19 00100010 hv-gen command page; select temperature coefficient 2 tc[2:0] = 010 20 10000000 control byte; co=1; rs=0 21 00000111 hv-gen command page; select high v lcd programming range (prs = 1); voltage multiplier off (hve = 1) 22 10000000 control byte; co=1; rs=0
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 43 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver 23 10100000 hv-gen command page; set v lcd =7.71v; vop[6:0] = 0100000 24 01000000 control byte; co=0; rs=1 25 00011111 data write; yandx are initialized to 0 by default, so they are not set here 26 00000101 data write 27 00000111 data write 28 00000000 data write 29 00011111 data write 30 00000100 data write 31 00011111 data write; last data and stop transmission 32 011110sa00 repeated start; slave address; r/w =0 table 17. programming example for pcf8531 ?continued step serial bus byte display operation db7 db6 db5 db4 db3 db2 db1 db0 mgs40 5 mgs40 6 mgs40 7 mgs40 7 mgs40 9 mgs41 0 mgs41 1 mgs41 1
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 44 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver 33 10000000 control byte; co=1; rs=0 34 00000001 h[1:0] indepe ndent command; select function and ram command page h[1:0] = 00 35 10000000 control byte; co=1; rs=0 36 00001001 function and ram command page; select display setting command page h[1:0] = 01 37 10000000 control byte; co=1; rs=0 38 00000001 h[1:0] indepe ndent command; select function and ram command page h[1:0] = 00 39 10000000 control byte; co=1; rs=0 40 00001101 display control; set inverse video mode (d = 1; e = 1 and im = 0) 41 10000000 control byte; co=1; rs=0 42 10000000 set x address of ram; set address to ?0000000? 43 01000000 control byte; co=0; rs=1 44 00000000 data write table 17. programming example for pcf8531 ?continued step serial bus byte display operation db7 db6 db5 db4 db3 db2 db1 db0 mgs41 1 mgs41 1 mgs41 2 mgs41 2 mgs41 2 mgs41 2 mgs41 4
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 45 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver 16. package outline not applicable. 17. handling information all input and output pins are protected ag ainst electrostatic discharge (esd) under normal handling. when handling metal-oxide semiconductor (mos) devices ensure that all normal precautions are taken as described in jesd625-a , iec 61340-5 or equivalent standards. 18. packing information table 18. tray dimensions (see figure 34 ) symbol description value a pocket pitch in x direction 13.72 mm b pocket pitch in y direction 4.17 mm c pocket width in x direction 12.34 mm d pocket width in y direction 2.05 mm e tray width in x direction 50.8 mm f tray width in y direction 50.8 mm x number of pockets, x direction 3 y number of pockets, y direction 10 fig 34. tray details mgs488 d c a x y f e b
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 46 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver 19. abbreviations the orientation of the ic in a pocket is indica ted by the position of the ic type name on the die surface with respect to the chamfer on the upper left corner of the tray. refer to the bonding pad location diagram ( figure 2 ) for the orientation and position of the type name on the die surface. fig 35. tray alignment mgs48 9 pcf8531 table 19. abbreviations acronym description cdm charged device model cmos complementary metal-oxide semiconductor cog chip-on-glass ddram double data random access memory emc electromagnetic compatibility esd electrostatic discharge hbm human body model hv high voltage ic integrated circuit ito indium tin oxide lcd liquid crystal display lsb least significant bit mm machine model mpu microprocessor unit por power-on reset ram random access memory rc resistance-capacitance tc temperature coefficient scl serial clock line sda serial data line
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 47 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver 20. references [1] an10170 ? design guidelines for cog modules with nxp monochrome lcd drivers [2] an10706 ? handling bare die [3] an10853 ? esd and emc sensitivity of ic [4] iec 60134 ? rating systems for electronic tu bes and valves and analogous semiconductor devices [5] iec 61340-5 ? protection of electronic devices from electrostatic phenomena [6] jesd22-a114 ? electrostatic discharge (esd) sensitivity testing human body model (hbm) [7] jesd22-a115 ? electrostatic discharge (esd) se nsitivity testing machine model (mm) [8] jesd78 ? ic latch-up test [9] jesd625-a ? requirements for handling elec trostatic-discharge-sensitive (esds) devices [10] nx3-00092 ? nxp store and transport requirements [11] um10204 ? i 2 c-bus specification and user manual
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 48 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver 21. revision history table 20. revision history document id release date data sheet status change notice supersedes pcf8531 v.6 20110516 product data sheet - pcf8531 v.5 modifications: ? specified for product type pcf8531u/2da/1 pcf8531 v.5 20100810 product data sheet - pcf8531_4 pcf8531_4 20080613 product data sheet - pcf8531_3 pcf8531_3 20000211 product data sheet - pcf8531_2 pcf8531_2 19990810 product data sheet - pcf8531_sds_1 pcf8531_sds_1 19990322 product data sheet - -
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 49 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver 22. legal information 22.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 22.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 22.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
pcf8531 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 16 may 2011 50 of 51 nxp semiconductors pcf8531 34 x 128 pixel matrix driver non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive s pecifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully in demnifies nxp semi conductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive appl ications beyond nxp semiconductors? standard warranty and nxp semicond uctors? product specifications. bare die ? all die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the nxp semiconductors storage and transportation conditions. if there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. there are no post-packing tests performed on individual die or wafers. nxp semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. accordingly, nxp semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. it is the responsibility of the customer to test and qualify their application in which the die is used. all die sales are conditioned upon and subject to the customer entering into a written die sale agreement with nxp semiconductors through its legal department. 22.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 23. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors pcf8531 34 x 128 pixel matrix driver ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 16 may 2011 document identifier: pcf8531 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 24. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 functional description . . . . . . . . . . . . . . . . . . 14 7.1 oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2 power-on reset (por) . . . . . . . . . . . . . . . . . 14 7.3 i 2 c-bus controller . . . . . . . . . . . . . . . . . . . . . . 14 7.4 input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.5 display data ram . . . . . . . . . . . . . . . . . . . . . . 14 7.6 timing generator. . . . . . . . . . . . . . . . . . . . . . . 14 7.7 address counter . . . . . . . . . . . . . . . . . . . . . . . 14 7.8 display address counter . . . . . . . . . . . . . . . . . 14 7.9 command decoder . . . . . . . . . . . . . . . . . . . . . 14 7.10 bias voltage generator . . . . . . . . . . . . . . . . . . 15 7.11 v lcd generator . . . . . . . . . . . . . . . . . . . . . . . . 15 7.12 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.13 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.14 column driver outputs. . . . . . . . . . . . . . . . . . . 15 7.15 row driver outputs . . . . . . . . . . . . . . . . . . . . . 15 8 lcd waveforms and ddram to data mapping . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.1 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9.2 function set . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.2.1 pd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.2.2 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.3 set y address . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.4 set x address . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.5 set multiplex rate . . . . . . . . . . . . . . . . . . . . . . 21 9.6 display control (d, e, and im). . . . . . . . . . . . . 21 9.7 set bias system . . . . . . . . . . . . . . . . . . . . . . . 22 9.8 lcd bias voltage . . . . . . . . . . . . . . . . . . . . . . 23 9.9 set v lcd value . . . . . . . . . . . . . . . . . . . . . . . . 23 9.10 voltage multiplier control s[1:0] . . . . . . . . . . . 24 9.11 temperature compensation . . . . . . . . . . . . . . 24 10 i 2 c-bus interface . . . . . . . . . . . . . . . . . . . . . . . 28 10.1 characteristics of the i 2 c-bus. . . . . . . . . . . . . 28 10.1.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.1.2 start and stop conditions . . . . . . . . . . . . . 28 10.1.3 system configuration . . . . . . . . . . . . . . . . . . . 28 10.1.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 29 10.2 i 2 c-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 30 10.3 command decoder . . . . . . . . . . . . . . . . . . . . 31 11 internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 32 12 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 33 13 static characteristics . . . . . . . . . . . . . . . . . . . 34 14 dynamic characteristics. . . . . . . . . . . . . . . . . 35 15 application information . . . . . . . . . . . . . . . . . 39 15.1 typical system configuratio n . . . . . . . . . . . . . 39 15.2 power supply connections for internal v lcd generation . . . . . . . . . . . . . . . . . . . . . . . 39 15.3 power supply connections for external v lcd generation . . . . . . . . . . . . . . . . . . . . . . . 40 15.4 information about v lcd connections . . . . . . . 40 15.5 chip-on-glass application. . . . . . . . . . . . . . . . 41 15.6 programming example. . . . . . . . . . . . . . . . . . 42 16 package outline. . . . . . . . . . . . . . . . . . . . . . . . 45 17 handling information . . . . . . . . . . . . . . . . . . . 45 18 packing information . . . . . . . . . . . . . . . . . . . . 45 19 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 46 20 references. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 21 revision history . . . . . . . . . . . . . . . . . . . . . . . 48 22 legal information . . . . . . . . . . . . . . . . . . . . . . 49 22.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 49 22.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 22.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 49 22.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 50 23 contact information . . . . . . . . . . . . . . . . . . . . 50 24 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

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